As a surface mounting type package, BGA (Ball Grid Array) is typically known.
FIG. 9 is an illustrative sectional view showing a configuration of a semiconductor device which adopts the BGA. The semiconductor device includes a semiconductor chip 101, an interposer 102 equipped with the semiconductor chip 101, and a sealing resin 103. The sealing resin 103 seals the semiconductor chip 101 as well as a surface that opposes to the semiconductor chip 101 on the interposer 102.
The interposer 102 has a resin substrate 104 formed of an insulative resin as a base substrate and includes an island 105 and a plurality of internal terminals 106 on one side of the resin substrate 104. The island 105 is formed in a generally rectangular shape with a size greater than the semiconductor chip 101 as seen from top. The island 105 is bonded to the back surface of the semiconductor chip 101 with a bonding material 107. A plurality of internal terminals 106 are disposed around the island 105 and electrically connected by a bonding wire 108 to the electrode pad (not shown) on the front surface of the semiconductor chip 101 that is bonded to the island 105. On the other surface of the resin substrate 104, a plurality of ball shaped external terminals 109 are disposed in an aligned manner for electrically connected to a land on the mounting substrate (printed wiring board). The internal terminals 106 on one surface of the resin substrate 104 and the external terminals 109 on the other surface of the resin substrate 104 are electrically connected via a metal provided within a through hole (not shown) that extends from one surface to the other surface of the resin substrate 104.
In such semiconductor devices, an epoxy resin bonding adhesive, a silver paste, or an insulating paste is typically used as the bonding material 107 for bonding the semiconductor chip 101 to the island 105. Bonding materials using a soldering material have not been provided at present for this purpose.
For example, a semiconductor chip built with a power IC operates with the back surface (the back surface of a semiconductor substrate) serving as a ground. For this reason, in the case where a semiconductor chip built with the power IC is provided as the semiconductor chip 101 shown in FIG. 9, the islands 105 and the external terminals 109 are electrically connected, and at the same time, the back surface of the semiconductor chip 101 must be bonded to the islands 105 with an electrically conductive bonding material 107. However, in the case where the soldering material is employed as the bonding material 107, when the temperature of the semiconductor device changes rapidly or drops after the bonding under high temperatures, the peripheral portion on the back surface side of the semiconductor chip 101 may be applied with a stress from the bonding material 107 and this may cause damages such as crack at the peripheral portion. When the soldering material is employed as the bonding material 107, for example, a reflow soldering is absolutely required. During the cooling process after the reflow soldering, a difference in heat shrinkage amount is generated between the interposer 102 (resin substrate 104) and the semiconductor chip 101 and causes a stress. The stress caused by the difference in heat shrinkage amount is then transferred from the bonding material 107 to the peripheral portion on the back surface of the semiconductor chip 101.
Such problem also occurs in the case where a semiconductor chip is bonded with a soldering material to a dye pad of a lead frame having a relatively small thickness.
On the other hand, methods of die bonding a semiconductor chip include a method including the steps of forming a lead frame or a plating layer such as silver, palladium, and gold on the surface of the organic substrate or the like, applying solder thereto, using the applied solder as a bonding material, and then pressing and mounting a semiconductor chip to the bonding material.
Along with recent development of a highly integrated semiconductor chip, the advancement of a wire bonding technology has achieved a bonding pad having a smaller and finer pitch, and as a result, the number of wire bonding that is able to be connected in a semiconductor chip having an identical size, in other words, the number of the bonding wires required for wiring a single semiconductor chip, is in the increase.
Accordingly, this tends to cause various problems including: failures in wire bonding due to misalignment of a semiconductor chip, failures such as edge touch and short circuit due to the nonuniform loop-like shape of the bonding wire after the wire bonding process, or failures due to a narrow space between bonding wires. Consequently, a precise mounting positioning is required when mounting the semiconductor chip.
In order to solve these problems, the alignment process has been conventionally performed in such a way that two components to be aligned with each other are provided with a portion having a greater wettability and a portion having a less wettability, and the portion with greater wettability is applied with a liquid such as a bonding adhesive and is overlapped with the other component to change the relative position of the two components by way of the surface tension of the liquid (see Patent Document 2, for example).
With referring to FIGS. 10 (a) and 10 (b) and FIGS. 11 (a) through 11(d), the case in which the alignment method disclosed in Patent Document 2 is adopted as the die bonding process of the semiconductor chip will be described hereinafter.
FIG. 10(a) is a plan view schematically showing an example of an island used in the conventional die bonding process, and FIG. 10(b) is a longitudinal sectional view schematically showing the island.
As shown in FIGS. 10(a) and 10(b), on a part of the surface of an island 81, a solder-resist is applied and a solder-resist layer 84 is formed. A metal surface 83 is not applied with the solder-resist and the island 81 is exposed thereon, whereby the metal surface 83 is easily wet by solder. On the other hand, on the solder-resist layer 84 the solder is difficult to wet. The metal surface 83 has a square shape, which is identical with the shape of the back surface of the semiconductor chip which is subject to subsequent die bonding process.
FIGS. 11(a) through FIG. 11(d) are a flow chart schematically showing an example of conventional die bonding processes.
First, a solder 86 is applied on the metal surface 83 on the island 81 by using a metal mask as shown in FIG. 11(a). Then, a semiconductor chip 82 is pressed against the solder 86 for fixing the semiconductor chip 82 as shown in FIG. 11(b). Next, the solder 86 is heated to melt as shown in FIG. 11(c). The resultant molten solder 86a spreads over the entire bottom surface of the semiconductor chip 82 and then the semiconductor chip 82 moves under the influence of a surface tension toward a direction in which the metal surface 83 and the semiconductor chip 82 are opposed to each other, as shown in FIG. 11(c). With this movement, the metal surface 83 of the island 81 and the semiconductor chip 82 are opposed to each other as shown in FIG. 11(d), and the alignment is complete.
In accordance with the process mentioned above, the formation of the solder-resist layer 84 on a particular portion of the island 81 can provide two separate portions: one portion where the solder 86 does not wet (solder-resist layer 84) and the other portion where the solder 86 easily wets (metal surface 83). Under the influence of surface tension which acts to minimize the surface area of the droplet, the molten solder 86a pull the semiconductor chip 82 onto the metal surface 83 which is a target mounting position of the semiconductor chip 82. The metal surface 83 on the island 81 and the semiconductor chip 82 are thus opposed with each other to perform the alignment.
However, as the semiconductor chip 82 moves in a manner to oppose to the metal surface 83 under the influence of surface tension of the molten solder 86a, the difference between the surface area of the molten solder 86a that is on the move and the surface area of the molten solder 86a that is in an opposed state gradually becomes smaller. Accordingly, the force to attract the semiconductor chip 82 by the action of surface tension gradually becomes weaker. Accordingly, due to the resistance force and the like that are caused by the viscosity of the solder, there exists some cases where it is impossible for the semiconductor chip 82 to move to a predetermined target position, and also there exists a problem that the semiconductor chip 82 cannot move precisely to a target position on the island 81.    Patent Document 1: Japanese Unexamined Patent Publication No. 2001-181563    Patent Document 2: Japanese Unexamined Patent Publication No. 2001-087953